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IC-NQ
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev D1, Page 1/25 FEATURES o Resolution of up to 8192 angle steps per sine/cosine period o Binary and decimal resolution settings, e.g. 500, 512, 1000, 1024; programmable angle hysteresis o Conversion time of just 250 ns including amplifier settling o Count-safe vector follower principle, realtime system with 70 MHz sampling rate o Direct sensor connection; selectable input gain o Front-end signal conditioning features offset (8 bit), amplitude ratio (5 bit) and phase (6 bit) calibration o 250 kHz input frequency o Parameterization and absolute angle output via bidirectional high-speed synchronous-serial BiSS Interface (B protocol) o A QUAD B incremental outputs with selectable minimum transition distance (e.g. 0.25 s for 1 MHz at A) o Index signal processing adjustable in position and width o Fault monitoring: frequency, amplitude, configuration (CRC) o Multiturn counting to 8 bit or 24 bit o Fully re-programmable by BiSS interface with access to serial EEPROM to store setup o ESD protection and TTL-/CMOS-compatible outputs APPLICATIONS o Interpolator IC for position data acquisition from analog sine/cosine sensors o Optical linear/rotary encoders o MR sensor systems
PACKAGES
TSSOP20
BLOCK DIAGRAM
Copyright (c) 2002, 2009 iC-Haus
http://www.ichaus.com
IC-NQ
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev D1, Page 2/25 DESCRIPTION IC-NQ is a monolithic A/D converter which, by applying a count-safe vector follower principle, converts sine/cosine sensor signals with a selectable resolution and hysteresis into angle position data. This absolute value is output via a high-speed synchronousserial BiSS interface and trails a master clock rate of up to 10 Mbit/s, or, alternatively, can be set so that it is compatible with SSI. A period counter supplements the position data with a multiturn count and can be configured for BiSS single-cycle data output. At the same time any changes in output data are converted into incremental A QUAD B encoder signals. Here, the minimum transition distance can be adapted to suit the system on hand (cable length, external counter). A synchronised zero index is generated and output to Z if enabled by the PZERO and NZERO inputs. The front-end amplifiers are configured as instrumentation amplifiers, permitting sensor bridges to be directly connected without the need for external resistors. Various programmable D/A converters are available for the conditioning of sine/cosine sensor signals with regard to offset, amplitude ratio and phase errors. Front-end gain can be set in stages graded to suit all common differential sensor signals from approximately 20 mVpp to 1.5 Vpp, and also singleended sensor signals from 40 mVpp to 3 Vpp respectively. Two serial interfaces have been included to permit configuration of the device, connection of an EEPROM or synchronous-serial data transfer (BiSS). Both interfaces are bidirectional and enable the complete configuration of the device including the transfer of setup and system data to the EEPROM for permanent storage. If the memory is detected following a power-down reset, the chip setup is read in and automatically repeated if a CRC error occurs.
IC-NQ
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev D1, Page 3/25 CONTENTS PACKAGES ABSOLUTE MAXIMUM RATINGS THERMAL DATA ELECTRICAL CHARACTERISTICS CHARACTERISTICS: Diagrams . . . . . . . OPERATING REQUIREMENTS: BiSS and SSI Interface PARAMETER and REGISTER SIGNAL CONDITIONING CONVERTER FUNCTIONS MAXIMUM POSSIBLE CONVERTER FREQUENCY Serial data output ............... Incremental output to A, B and Z . . . . . . . 4 5 5 6 8 INCREMENTAL SIGNALS SIGNAL MONITORING and ERROR MESSAGES TEST FUNCTIONS BiSS INTERFACE Protocol and Data Format . . . . . Sensor Data Communication . . . Register Data Communication . . Sensor Data Output in SSI Format Examples of SSI formats . . . . . EEPROM INTERFACE APPLICATION HINTS Principle Input Circuits . . . . . . . . . . . . . Basic circuit . . . . . . . . . . . . . . . . . . . EVALUATION BOARD DESIGN REVIEW: Notes On Chip Functions 15
17 18 19 19 20 20 21 21 21 22 22 23 23 24
8 10 11 12
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13 13 14
IC-NQ
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev D1, Page 4/25 PACKAGES TSSOP20 (according to JEDEC Standard) PIN CONFIGURATION TSSOP20 4.4 mm, lead pitch 0.65 mm PIN FUNCTIONS No. Name Function Input Cosine + Input Cosine +5 V Supply Voltage (analog) Ground (analog) Reference Voltage Output Incremental Output A Analog signal COS+ (TMA mode) PWM signal for Offset Sine (Calib.) 7B Incremental Output B Analog signal COS- (TMA mode) PWM signal for Offset Cosine (Calib.) 8Z Output Index Z PWM signal for Phase/Ratio (Calib.) 9 GND Ground 10 VDD +5 V Supply Voltage (digital) 11 SLI BiSS interface, data input 12 MA BiSS interface, clock line 13 SLO BiSS interface, data output 14 SDA EEPROM interface, data line Analog signal SIN+ (TMA mode) 15 SCL EEPROM interface, clock line Analog signal SIN- (TMA mode) 16 NERR Error Input/Output, active low 17 PZERO Input Zero Signal + 18 NZERO Input Zero Signal 19 PSIN Input Sine + 20 NSIN Input Sine External connections linking VDDA to VDD and GND to GNDA are required. *) If only a single IC-NQ device and no BiSS chain circuitry is used, pin SLI can remain unwired or can be linked to ground (GND). 1 2 3 4 5 6 PCOS NCOS VDDA GNDA VREF A
IC-NQ
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev D1, Page 5/25 ABSOLUTE MAXIMUM RATINGS
These ratings do not imply operating conditions; functional operation is not guaranteed. Beyond these ratings device damage may occur. Item No. Symbol Parameter Analog Supply Voltage Digital Supply Voltage V() < VDDA + 0.3 V V() < VDD + 0.3 V Conditions Min. -0.3 -0.3 -0.3 Max. 6 6 6 V V V Unit
G001 VDDA G002 VDD G003 Vpin()
Voltage at PSIN, NSIN, PCOS, NCOS, PZERO, NZERO, VREF, NERR, SCL, SDA, MA, SLI, SLO, A, B, Z G004 Imx(VDDA) Current in VDDA G005 Imx(GNDA) Current in GNDA G006 Imx(VDD) G008 Imx() Current in VDD Current in PSIN, NSIN, PCOS, NCOS, PZERO, NZERO, VREF, NERR, SCL, SDA, MA, SLI, SLO, A, B, Z Pulse Current in all pins (Latch-up Strength) G007 Imx(GND) Current in GND
-50 -50 -50 -50 -10
50 50 50 50 10
mA mA mA mA mA
G009 Ilu()
according to Jedec Standard No. 78; Ta = 25 C, pulse duration 10 ms, VDDA = VDDAmax , VDD = VDDmax , Vlu() = (-0.5...+1.5) x Vpin()max HBM 100 pF discharged through 1.5 k
-100
100
mA
G010 Vd() G011 Tj G012 Ts
ESD Susceptibility at all pins Junction Temperature Storage Temperature Range
2 -40 -40 150 150
kV C C
THERMAL DATA
Operating Conditions: VDDA = VDD = 5 V 10 % Item No. T01 Symbol Ta Parameter Operating Ambient Temperature Range TSSOP20 ET -40/125 Conditions Min. -25 -40 Typ. Max. 85 125 C C Unit
All voltages are referenced to ground unless otherwise stated. All currents into the device pins are positive; all currents out of the device pins are negative.
IC-NQ
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev D1, Page 6/25 ELECTRICAL CHARACTERISTICS
Operating Conditions: VDDA = VDD = 5 V 10 %, Tj = -40 ... 125 C, unless otherwise stated Item No. 001 002 003 004 005 006 Symbol Parameter Conditions Min. VDDA, VDD I(VDDA) I(VDD) Von Vhys Vc()hi Permissible Supply Voltage Supply Current in VDDA Supply Current in VDD Turn-on Threshold VDDA, VDD Turn-on Threshold Hysteresis Clamp Voltage hi at PSIN, NSIN, PCOS, NCOS, PZERO, NZERO, VREF Vc()hi = V() - VDDA; I() = 1 mA, other pins open fin() = 200 kHz; A, B, Z open fin() = 200 kHz; A, B, Z open 3.2 200 0.3 1.6 4.5 Typ. Max. 5.5 15 20 4.4 V mA mA V mV V Unit
Total Device
007
Vc()lo
Clamp Voltage lo at I() = -1 mA, other pins open PSIN, NSIN, PCOS, NCOS, PZERO, NZERO, VREF, NERR, SCL, SDA, MA, SLI, SLO, A, B, Z Clamp Voltage hi at NERR, SCL, SDA, MA, SLI, SLO, A, B, Z Vc()hi = V() - VDD; I() = 1 mA, other pins open
-1.6
-0.3
V
008
Vc()hi
0.3
1.6
V
Input Amplifiers PSIN, NSIN, PCOS, NCOS 101 Vos() Input Offset Voltage
Vin() and G() in accordance with table Gain Select; G 20 G < 20 see 101 V() = 0 V ... VDDA G() in accordance with table Gain Select G() in accordance with table Gain Select G = 80 G = 2.667 G = 80 G = 2.667
-10 -15 10 -50 95 97 230 650 4 9 -1.0 -0.5 -10 0.35
10 15
mV mV V/K
102 103 104 105 106 107
TCos Iin() GA GArel fhc SR
Input Offset Voltage Temperature Drift Input Current Gain Accuracy Gain SIN/COS Ratio Accuracy Cut-off Frequency Slew Rate
50 102 103
nA % % kHz kHz V/s V/s
Sin/D Conversion: Accuracy 201 202 203 AAabs AAabs AArel Absolute Angle Accuracy without referred to 360 input signal, G = 2.667, calibration Vin = 1.5 Vpp, HYS = 0 Absolute Angle Accuracy after calibration Relative Angle Accuracy referred to 360 input signal, HYS = 0, internal signal amplitude of 2 ... 4 Vpp referred to output signal period of A/B, G = 2.667, Vin = 1.5 Vpp, SELRES = 1024, FCTR = 0x0004 ... 0x00FF, fin < finmax (see table 14) I(VREF) = -1 mA ... +1 mA 1.0 +0.5 10 DEG DEG %
Reference Voltage VREF 801 VREF Reference Voltage 48 52 % VDDA
Oscillator A01 fosc()
Oscillator Frequency
presented at SCL with subdivision of 2048; VDDA = VDD = 5 V 10 % VDDA = VDD = 5 V VDDA = VDD = 5 V
52 60
72 -0.1 +10.6
90 83
MHz MHz %/K %/V
A02 A03
TCosc VCosc
Oscillator Frequency Temperature Drift Oscillator Frequency Power Supply Dependance
IC-NQ
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev D1, Page 7/25 ELECTRICAL CHARACTERISTICS
Operating Conditions: VDDA = VDD = 5 V 10 %, Tj = -40 ... 125 C, unless otherwise stated Item No. B01 B02 B03 B04 Symbol Parameter Conditions Min. Vos() Iin() Vcm() Vdm() Input Offset Voltage Input Current Common-Mode Input Voltage Range Differential Input Voltage Range Saturation Voltage hi Saturation Voltage lo Rise Time Fall Time Permissible Load at A, B Threshold Voltage hi Threshold Voltage lo Hysteresis Pull-up Current in MA Pull-down Current in SLI Permissible Clock Frequency at MA Vt()hys = Vt()hi - Vt()lo V() = 0 ... VDD - 1 V V() = 1 ... VDD SSI protocol BiSS B protocol: sensor mode BiSS B protocol: register mode 10 0 0 1 0.8 300 -240 20 -120 120 -25 300 4 10 0.25 50 0 2 1.5 2 0.8 Vt()hys = Vt()hi - Vt()lo 300 5 20 I() = 4 mA V() = 0 ... VDD - 1 V CL() = 50 pF MA = hi, no BiSS access, amplitude or frequeny error 10 60.7 1 -600 -300 7 100 0.45 -75 60 ms ms V V mV ms kHz V A ns ms ms M Vs()hi = VDD - V(); I() = -4 mA I() = 4 mA CL() = 50 pF CL() = 50 pF TMA = 1 (calibration mode) 1 2 V() = Vcm() V() = 0 V ... VDDA -20 -50 1.4 0 Typ. Max. 20 50 VDDA1.5 VDDA 0.4 0.4 60 60 mV nA V V V V ns ns M V V mV A A MHz MHz MHz ns Unit
Zero Comparator
Incremental Outputs A, B, Z and BiSS Interface Output SLO D01 Vs()hi D02 Vs()lo D03 tr() D04 tf() D05 RL() E01 E02 E03 E04 E05 E06 Vt()hi Vt()lo Vt()hys Ipu(MA) Ipd(SLI) fclk(MA)
BiSS Interface: Inputs MA, SLI
E07 E08 E09 E10 F01 F02 F03 F04
tp(MASLO) tbusy()s tbusy()r tidle() Vt()hi Vt()lo Vt()hys tbusy()cfg
Propagation Delay: MA edge vs. all modes, RL(SLO) 1 k SLO output Processing Time Sensor Mode Processing Time Register Mode Interface Blocking Time Threshold Voltage hi Threshold Voltage lo Hysteresis Duration of Startup Configuration error free EEPROM access Write/Read Clock at SCL Saturation Voltage lo Pull-up Current Fall Time Error Signal Indication Time at NERR (lo signal) delay of start bit delay of start bit with read access to EEPROM powering up with no EEPROM
EEPROM Interface, Control Logic: Inputs SDA, NERR
EEPROM Interface, Control Logic: Outputs SDA, SCL, NERR G01 f() G02 Vs()lo G03 Ipu() G04 ft() G05 tmin()lo G06 Tpwm() G07 RL()
Error Signal PWM Cycle Duration fosc() subdivided 222 at NERR Permissible Load at SDA, SCL TMA = 1 (calibration mode)
IC-NQ
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev D1, Page 8/25 CHARACTERISTICS: Diagrams
0% AArel 10%
40% 50%
60%
twhi()/T
0% AArel 10%
90% 100%
110%
Figure 1: Definition of relative angle error.
$ tMTD
Figure 2: Definition of minimum transition distance.
0.15 0.1 0.05 0 -0.05 -0.1 -0.15
0
90
180
270
360
Figure 3: Typical residual absolute angle error after calibration.
IC-NQ
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev D1, Page 9/25 OPERATING REQUIREMENTS: BiSS and SSI Interface
Operating Conditions: VDD = 5 V 10 %, Ta = -25 ... 85 C; input levels lo = 0 ... 0.45 V, hi = 2.4 V ... VDD Item No. Symbol Parameter Conditions Fig. Min. Permissible Clock Period Clock Signal Hi Level Duration Clock Signal Lo Level Duration Permissible Clock Period Clock Signal Hi Level Duration Clock Signal Lo Level Duration Permissible Clock Period Permissible Clock Halt (idle) Clock Signal Hi Level Duration Clock Signal Hi Level Duration Clock Signal Lo Level Duration "Logic 0" Hi Level Duration "Logic 1" Hi Level Duration read out of register data CFGTOR selected in accordance with table on page 15 CFGTOR selected in accordance with table on page 15 CFGTOS = 0x01 4 4 4 5 5 5 6 6 6 6 6 6 6 10 70 30 250 25 25 100 25 25 4 0 indefinite ttor 70 ttor 30 90 ns % TMAR ns % TMAR % TMAR ttos Max. 2x ttos ttos ttos ns ns ns ns ns ns s Unit
SSI Output (SELSSI = 1) I001 TMAS I002 tMASh I003 tMASl I004 TMAS I005 tMASh I006 tMASl I007 TMAR I008 tidle I009 tMARh I010 tMARh I011 tMARl I012 tMA0h I013 tMA1h
BiSS Sensor Mode
BiSS Register Mode
Figure 4: Timing diagram of SSI output.
Figure 5: Timing diagram of BiSS sensor mode.
Figure 6: Timing diagram of BiSS register mode.
IC-NQ
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev D1, Page 10/25 PARAMETER and REGISTER Register Description . . . . . . . . . . . . . . . . . . . . . . . Page 10 Signal Conditioning . . . . . . . . . . . . . . . . . . . . . . . Page 11 GAIN: Gain Select SINOFFS: Offset Calibration Sine COSOFFS: Offset Calibration Cosine REFOFFS: Offset Calibration Reference RATIO: Amplitude Calibration PHASE: Phase Calibration Converter Function . . . . . . . . . . . . . . . . . . . . . . . . Page 12 SELRES: Resolution HYS: Hysteresis FCTR: Max. Permissible Converter Frequency Incremental Signals . . . . . . . . . . . . . . . . . . . . . . . Page 15 CFGABZ: Output A, B, Z ROT: Direction of Rotation CBZ: Period Counter Configuration ENRESDEL: Output Turn-On Delay ZPOS: Zero Signal Position CFGZ: Zero Signal Length CFGAB: Zero Signal Logic OVERVIEW Adr
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07* 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F EEPROM 0x10 0x1F 0x20 0x77 0x78 0x7F 0x00 - 0xF 0x10 - 0x67 0x68 - 0x6F Reserved EEPROM register section storing IC-NQ device setup Free EEPROM registers EEPROM: BiSS Identifier, ROM: Device ID IC-NQ X3: 4E 51 58 33 {ADR0} 00 69 43** CRC(7:0) check sum over address 0-14 with CRC polynomial: "100100111" (read out of EEPROM) PHASE(5:0) SELAMPL GAIN(3:0) SINOFFS(7:0) COSOFFS(7:0) REFOFFS RATIO(4) AMPL(1:0) CFGTOR(1:0) CFGTOS(1:0) Reserved address / internal use RATIO(3:0) ENRESDEL
Signal Monitoring and Error Messages . . . . . . . . . . . . . . . . . . . . . . . Page 17 SELAMPL: Amplitude Monitoring, function AMPL: Amplitude Monitoring, thresholds AERR: Amplitude Error FERR: Frequency Error Test Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 18 TMODE: Test Mode TMA: Analog Test Mode BiSS Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 19 CFGTOS: Interface Timeout CFGTOR: Interface Timeout M2S: Period Counter Output BiSSMOD: Protocol Version SELSSI: CFGSSI: RPL: SSI Compatibility SSI Output Register Access Safety Level
Bit 7
BiSSMOD
Bit 6
M2S(1:0) HYS(2:0) SELSSI
Bit 5
Bit 4
Bit 3
Bit 2
SELRES(4:0) ZPOS(4:0)
Bit 1
Bit 0
ROT
CBZ FCTR(7:0)
CFGABZ(1:0) RPL(1:0) FCTR(14:8) TMODE(2:0)
CFGZ(1:0) AERR FERR
CFGSSI(1:0)
CFGAB(1:0)
TMA
As no access protections are selected all registers are accessible by read and write operations (see RPL). *) Programming to value 0x00 is recommended. **) IC-NQ V2: 4E 51 56 32 {Adr 0x00} 00 69 43
Table 5: Register layout
IC-NQ
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev D1, Page 11/25 SIGNAL CONDITIONING Input stages SIN and COS are configured as instrumentation amplifiers. The amplifier gain must be selected in accordance with the sensor signal level and
GAIN Adr 0x08, Bit 7:4 Sine/Cosine Input Signal Levels Vin() Amplitude Average value (DC) Single-ended Differential Single-ended up to 100 mVpp 0.7 V ... VDDA - 1.2 V 0.8 V ... VDDA - 1.2 V up to 120 mVpp 0.7 V ... VDDA - 1.2 V 0.8 V ... VDDA - 1.2 V up to 0.15 Vpp 0.7 V ... VDDA - 1.2 V 0.8 V ... VDDA - 1.2 V up to 0.2 Vpp 1.2 V ... VDDA - 1.2 V 1.3 V ... VDDA - 1.3 V up to 0.24 Vpp 1.2 V ... VDDA - 1.2 V 1.3 V ... VDDA - 1.3 V up to 0.28 Vpp 0.7 V ... VDDA - 1.2 V 0.8 V ... VDDA - 1.3 V up to 0.3 Vpp 1.2 V ... VDDA - 1.2 V 1.3 V ... VDDA - 1.3 V up to 0.4 Vpp 0.7 V ... VDDA - 1.2 V 0.8 V ... VDDA - 1.3 V up to 0.56 Vpp 1.2 V ... VDDA - 1.3 V 1.4 V ... VDDA - 1.4 V up to 0.8 Vpp 1.2 V ... VDDA - 1.3 V 1.4 V ... VDDA - 1.5 V up to 1 Vpp 0.8 V ... VDDA - 1.4 V 1.0 V ... VDDA - 1.6 V up to 1.2 Vpp 0.8 V ... VDDA - 1.4 V 1.1 V ... VDDA - 1.7 V up to 1.5 Vpp 0.9 V ... VDDA - 1.5 V 1.3 V ... VDDA - 1.9 V up to 2 Vpp 1.2 V ... VDDA - 1.6 V 1.7 V ... VDDA - 2.1 V up to 2.4 Vpp 1.2 V ... VDDA - 1.7 V 1.8 V ... VDDA - 2.3 V up to 3 Vpp 1.3 V ... VDDA - 1.8 V 2.0 V ... VDDA - 2.6 V
programmed to register GAIN according to the following table. Half of the supply voltage is output to VREF as center voltage to help DC level adaptation.
Code 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00
Amplification 80.000 66.667 53.333 40.000 33.333 28.571 26.667 20.000 14.287 10.000 8.000 6.667 5.333 4.000 3.333 2.667
Differential up to 50 mVpp up to 60 mVpp up to 75 mVpp up to 0.1 Vpp up to 0.12 Vpp up to 0.14 Vpp up to 0.15 Vpp up to 0.2 Vpp up to 0.28 Vpp up to 0.4 Vpp up to 0.5 Vpp up to 0.6 Vpp up to 0.75 Vpp up to 1 Vpp up to 1.2 Vpp up to 1.5 Vpp
Table 6: Gain Select
SINOFFS COSOFFS Code 0x00 0x01 ... 0x7F 0x80 0x81 ... 0xFF Notes Adr 0x09, Bit 7:0 Adr 0x0A, Bit 7:0 Output Offset 0V -7.8125 mV ... -0.9922 V 0V +7,8125 mV ... +0.9922 V Input Offset 0V -7.8125* mV / GAIN ... -0.9922 V / GAIN 0V +7.8125 mV / GAIN ... +0.9922 V / GAIN PHASE Code 0x00 0x01 ... 0x12 ... 0x1F Adr 0x0B, Bit 7:2 Phase Shift 90 90.703125 ... 102.65625 102.65625 102.65625 Code 0x20 0x21 ... 0x32 ... 0x3F Phase Shift 90 89.296875 ... 77.34375 77.34375 77.34375 RATIO Code 0x00 0x01 ... 0x0F Adr 0x0B, Bit 0, Adr 0x08, Bit 3:0 COS / SIN 1.0000 1.0067 ... 1.1 Code 0x10 0x11 ... 0x1F COS / SIN 1.0000 0.9933 ... 0.9000
Table 9: Amplitude Calibration
*) With REFOFFS = 0x00 und VDDA = 5 V.
Table 7: Offset Calibration Sine/Cosine
REFOFFS Code 0x00 0x01 Adr 0x0B, Bit 1 Reference Voltage Depending on VDDA (example of application: MR sensors) Not depending on VDDA (example of application: Sin/Cos encoders)
Table 10: Phase Calibration
Table 8: Offset Calibration Reference
IC-NQ
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev D1, Page 12/25 CONVERTER FUNCTIONS
SELRES Code Adr 0x00, Bit 4:0 Binary Resolutions 8192 4096 2048 1024 512 256 128 64 32 16 8 158 Hz, 635 Hz 317 Hz, 1.27 kHz 634 Hz, 2.54 kHz 1.27 kHz, 5.1 kHz 2.54 kHz, 10.2 kHz 5.1 kHz, 20.3 kHz 10.2 kHz, 40.6 kHz 20.3 kHz, 81.3 kHz 40.6 kHz, 162.5 kHz 81.3 kHz (max. 250 kHz @ 0x4202) 162 kHz (max. 250 kHz @ 0x4102) Examples of Permissible Input Frequencies finmax (FCTR 0x0004, 0x4304) SELRES Code Adr 0x00, Bit 4:0 Decimal Resolutions 2000 1600 1000 800 500 400 250 *1 125 *1,2 320 160 *2 80 *4 40 *8 200 100 *2 50 *1,4 25 *1,8
*1 *2,4,8
Examples of Permissible Input Frequencies finmax (FCTR 0x0004, 0x4304) 650 Hz, 2.6 kHz 812 Hz, 3.3 kHz 1.3 kHz, 5.2 kHz 1.6 kHz, 6.5 kHz 2.6 kHz, 10.4 kHz 3.2 kHz, 13 kHz 5.2 kHz, 20.8 kHz 5.2 kHz, 20.8 kHz 4.1 kHz, 16.3 kHz 4.1 kHz, 16.3 kHz 4.1 kHz, 16.3 kHz 4.1 kHz, 16.3 kHz 6.5 kHz, 26 kHz 6.5 kHz, 26 kHz 6.5 kHz, 26 kHz 6.5 kHz, 26 kHz
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F
0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F Notes
Not useful with increment A quad B output.
Table 11: Binary Resolutions
The internal converter resolution is higher by factor 2, 4 or 8.
Table 12: Decimal Resolutions
HYS Code 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 Adr 0x01, Bit 7:5 Hysteresis in degree 0 0.0879 0.1758 0.3516 0.7031 1.4063 5.625 45 1 LSB @ 12 bit 1/2 LSB @ 10 bit 1 LSB @ 10 bit 1/2 LSB @ 8 bit 1 LSB @ 8 bit only recommended for calibration 0.044 0.088 0.176 0.352 0.703 2.813 22.5 Hysteresis in LSB Absolute error*
Notes
*) The absolute error is equivalent to one half the angle hysteresis
Table 13: Hysteresis
IC-NQ
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev D1, Page 13/25 MAXIMUM POSSIBLE CONVERTER FREQUENCY The converter frequency automatically adjusts to the value necessary for the input frequency and resolution. This value ranges from zero to a maximum dependent on the oscillator frequency which can be set using register FCTR. Serial data output For BiSS or SSI output the maximum possible converter frequency can be adjusted to suit the maximum input frequency; an automatic converter resolution step-down feature can be enabled via the FCTR register. Should the input frequency exceed the frequency limit of the selected converter resolution, the LSB is kept stable and not resolved any further; the interpolation resolution halves. If the next frequency limit is overshot, the LSB and the LSB+1 are kept stable and so on. When the input frequency again sinks below this frequency limit, the fine resolution automatically returns.
Examples* finmax [kHz] at resol. 8192 1024 200 0.16 1.27 6.5 0.26 2.1 10.8 0.53 4.2 21.6 0.64 5.1 26.0 1.1 8.5 2.1 16.9 4.2 33.8 8.5 67.7 16.9 135 33.8 250 67.7 135 -
Max. Possible Converter Frequency For Serial Data Output Resolution Protocol Max. Input Frequency Restrictions Requirements at high input frequencies FCTR Min. Res. bin dec BiSS SSI finmax 0x0004 X X X X f(OSC)min / 40 / Resolution - 0x4102 8 X X X X f(OSC)min / 24 / Resolution Rel. angle error 2x increased 0x4202 16 X X X X 2 x f(OSC)min / 24 / Res. Rel. angle error 4x increased 0x4304 32 X X X X 4 x f(OSC)min / 40 / Res. Rel. angle error 8x increased 0x4602 64 X X X 4 x f(OSC)min / 24 / Res. Resolution lowered by factor of 2 0x4A02 128 X X X 8 x f(OSC)min / 24 / Res. Res. lowered by factor of 2-4 0x4E02 256 X X X 16 x f(OSC)min / 24 / Res. Res. lowered by factor of 2-8 0x5202 512 X X X 32 x f(OSC)min / 24 / Res. Res. lowered by factor of 2-16 0x5602 1024 X X X 64 x f(OSC)min / 24 / Res. Res. lowered by factor of 2-32 0x5A02 2048 X X X 128 x f(OSC)min / 24 / Res. Res. lowered by factor of 2-64 0x5E02 4096 X X X 256 x f(OSC)min / 24 / Res. Res. lowered by factor of 2-128 0x6202 8192 X X X 512 x f(OSC)min / 24 / Res. Res. lowered by factor of 2-256 Notes *) Calculated with fosc()min taken from Electrical Characteristics item A01.
Table 14: Maximum converter frequency for serial data output.
IC-NQ
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev D1, Page 14/25 Incremental output to A, B and Z There are two criteria which must be considered when setting the maximum possible converter frequency via the FCTR register: 1. The maximum input frequency 2. System limitations, e.g. due to slow counters or cable transmission nals. A digital zero-delay glitch filter then takes care of a temporal edge-to-edge separation, guaranteeing spike-free output signals after an ESD impact to the sensor, for instance. A serial data output is simultaneously possible at any time, using the BiSS or SSI protocol. However, for the transfer of angle data to the output register the incremental output is halted for one period of the clock signal applied to pin MA.
When facing system limitations it is useful to preselect a minimum transition distance for the output sig1. Max. Possible Converter Frequency Defined By The Maximum Input Frequency Output Frequency Resolution Maximum Input Frequency Restrictions fout @ finmax Requirem. at high input frequencies FCTR A, B bin dec finmax 0x0004 325 kHz X X f(OCS)min / 40 / Resolution None 0x4102 542 kHz X X f(OSC)min / 24 / Resolution Relative angle error 2x increased 0x4202 1.08 MHz X X 2 x f(OSC)min / 24 Res. Relative angle error 4x increased 0x4304 1.3 MHz X X 4 x f(OSC)min / 40 / Res. Relative angle error 8x increased Notes *) Calculated with fosc()min taken from Electrical Characteristics item A01. Examples* finmax [kHz] at resol. 8192 1024 200 0.16 1.27 6.5 0.26 2.1 10.8 0.53 4.2 21.6 0.64 5.1 26.0
Table 15: Max. converter frequency for incremental A/B/Z output, defined by the max. input frequency
2. Max. Possible Converter Frequency Defined By The Minimum Transition Distance Output Frequency Resolution Minimum Transition Distance Restrictions Example* fout @ tMTD Requirem. at A, B at high input frequencies tMTD [sec] FCTR A, B bin dec tMTD 0x00FF 10 kHz X X 2048 / f(OSC)max None 22.8 0x00FE 10.05 kHz X X 2040 / f(OSC)max None 22.7 0x00FD 10.09 kHz X X 2032 / f(OSC)max None 22.6 ... ... ... ... ... ... ... 0x0006 366 kHz X X 56 / f(OSC)max None 0.62 0x0005 427 kHz X X 48 / f(OSC)max None 0.53 0x0004 512 kHz X X 40 / f(OSC)max None 0.44 0x4102 854 kHz X X 24 / f(OSC)max Relative angle error 2x increased 0.27 0x4202 1.7 MHz X X 12 / f(OSC)max Relative angle error 4x increased 0.13 0x4304 2.1 MHz X X 10 / f(OSC)max Relative angle error 8x increased 0.11 Notes *) Calculated with fosc()max taken from El.Char. item A01; the min. transition distance refers to output A vs. output B without reversing the sense of rotation.
Table 16: Max. converter frequency for incremental A/B/Z output, defined by the min. transition distance
IC-NQ
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev D1, Page 15/25 INCREMENTAL SIGNALS
CFGABZ Code 0x00 0x01 0x02
Adr 0x02, Bit 3:2 Mode Normal Control signals for external period counters Calibration mode
OFFS SIN OFFS COS 1.1 0.9
PHASE 1.1 0.9
A A CA
B B CB
Z Z CZ
The following settings are required additionally: SELRES = 0x0D ZPOS = 0x00 HYS = 0x07 ROT = 0x00 AERR = 0x00 0x03 Calibration mode
+...V -...V
Figure 7: Offset
SIN*
OFFS SIN
Figure 8: Offset
COS*
OFFS COS 1.1 0.9
Figure 9: Phase*
RATIO 1.1 0.9
The following settings are required additionally: SELRES = 0x0D ZPOS = 0x00 HYS = 0x07 ROT = 0x00 AERR = 0x00 Notes
+...V -...V
Figure 10: Offset
SIN*
Figure 11: Offset
COS*
Figure 12: Amplitude*
*) Trimmed accurately when duty cycle is 50 %; Recommended trimming order (after selecting GAIN): Offset, Phase, Amplitude Ratio, Offset;
Table 17: Outputs A, B, Z
ROT Code 0x00 0x01 Adr 0x02, Bit 5 Direction Not inverted Inverted
SIN
Table 18: Direction of Rotation
COS
cw: F->0
CBZ Code 0x00 0x01
Adr 0x02, Bit 4 Clear by zero Disabled Enabled
FFFFFF
000000 ccw: 0->F
P(23:0)
A B Z
Table 19: Reset Enable for Period Counter
-180
-90
0
45
90
180
ENRESDEL
Adr 0x02, Bit 7 Output* immediately after 5 ms Function An external counter displays the absolute angle following power on. An external counter only displays changes vs. the initial power-on condition (moving halted to reapply power is precondition.)
Code 0x00 0x01
Figure 13: Clear by zero function of the period counter when enabled by CBZ = 1. Example for chip release IC-NQ V2 at resolution 64 (SELRES = 0x0A), zero signal at 45 (ZPOS = 0x04, CFGAB = 0x00) and the direction of rotation not inverted (ROT = 0x00, COS leads SIN).
Notes
*) Output delay after device configuration and internal reset.
Table 20: Output Turn-On Delay A, B, Z
IC-NQ
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev D1, Page 16/25
ZPOS Code 0x00 0x08 0x10 0x18 Adr 0x01, Bit 4:0 Chip versions IC-NQ X2, IC-NQ X3: Position 0 90 180 270 Chip version IC-NQ V2: Code 0x01 ... 0x1F Notes Position 11.25 (1 x 11.25) ... 348.75 (31 x 11.25) The zero signal is only output if released by the input pins (for instance with PZERO = 5 V, NZERO = VREF). CFGAB Code 0x00 0x01 0x02 0x03 CFGZ Code 0x00 0x01 0x02.. 03 Adr 0x02, Bit 1:0 Length 90 180 Synchronization
Table 22: Zero Signal Length
Adr 0x03, Bit 5:4 Z = 1 for B = 1, A = 1 B = 0, A = 1 B = 1, A = 0 B = 0, A = 0
Table 23: Zero Signal Logic
Table 21: Zero Signal Position
SIN
COS
A B Z (CFGZ= 0) Z (CFGZ= 1) Z (CFGZ= 2) -180 -90 0 45 90 180 Winkel
Figure 14: Incremental output signals for various length of the zero signal. Example for chip release IC-NQ V2 with resolution 64 (SELRES = 0x0A), a zero signal position of 45 (ZPOS = 0x04, CFGAB = 0x00) and no reversal of the rotational sense (ROT = 0x00, COS leads SIN).
IC-NQ
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev D1, Page 17/25 SIGNAL MONITORING and ERROR MESSAGES
SELAMPL AMPL Code 0x00 0x01 0x02 0x03 Code 0x04 0x05 0x06 0x07 Notes Adr 0x0C, Bit 2 Adr 0x0C, Bit 1:0 Max ( |Sin| , |Cos| ) Voltage threshold Vth 0.60 x VDDA 0.64 x VDDA 0.68 x VDDA 0.72 x VDDA Sin2 + Cos2 Vthmin Vthmax 0.48 0.68 x VDDA 0.56 0.76 x VDDA 0.64 0.84 x VDDA 0.72 0.92 x VDDA Output amplitude* 1.4 Vpp (0.28 x VDDA) 2.0 Vpp (0.40 x VDDA) 2.6 Vpp (0.51 x VDDA) 3.1 Vpp (0.62 x VDDA)
Vss Vth
Figure 15: Signal monitoring of minimum amplitude.
Output amplitude* 2.4 Vpp 3.4 Vpp 2.8 Vpp 3.8 Vpp 3.2 Vpp 4.2 Vpp 3.6 Vpp 4.6 Vpp
Vthmax Vthmin
*) Entries are calculated with VDDA = 5 V.
Table 24: Signal Amplitude Monitoring
Figure 16: Sin2 + Cos2 signal monitoring. Each phase in the configuration process is signaled by NERR = low; the signal is only reset following a successful CRC (cyclic redundancy check). If the data transfer from the EEPROM is faulty and the CRC unsuccessful, then the configuration phase is automatically repeated. The process aborts following a third unsuccessful attempt and the error message output remains set to low until a write access occurs at address 0 via the BiSS Interface (internal reset). To enable the successful diagnosis of faults other types of error are signaled at NERR using a PWM code as given in the key on the left. Two error bits are provided to enable communication via the BiSS Interface; these bits can decode four different types of error. If NERR is held at low by an external source, such as an error message from the system, for example, this can also be verified via the BiSS Interface. Error events are stored for the BiSS sensor data output and deleted afterwards. Errors at NERR are displayed for a minimum of ca. 10 ms, as far as no BiSS readout causes a deletion. If an error in amplitude occurs the conversion process is terminated and the incremental output signals halted. An error in amplitude rules out the possibility of an error in frequency.
AERR Code 0x00 0x01
Adr 0x03, Bit 1 Amplitude error message disabled enabled
Table 25: Amplitude Error
FERR Code 0x00 0x01 Note Adr 0x03, Bit 0 Excessive frequency error message disabled enabled Input frequency monitoring is operational for resolutions 16
Table 26: Frequency Error
Configuration Error Messaging always released
Table 27: Configuration Error
Error Keys Failure Mode No error Amplitude error Frequency error Configuration Undervoltage System error Pin NERR HI LO/HI = 75 % (AERR = 0: HI) LO/HI = 50 % (FERR = 0: HI) LO LO NERR = low caused by an external error signal Error bits E1, E0 with BiSS and SSI 11 01 (11) 10 (11) 00 00 00
Table 28: Error Keys
IC-NQ
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev D1, Page 18/25 TEST FUNCTIONS
TMODE Code 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 Condition Adr 0x06, Bit 3:1 Signal at Z Z A xor B ENCLK NLOCK CLK DIVC PZERO - NZERO TP CFGABZ = 0x00 Description no test mode Output A EXOR B iC-Haus device test iC-Haus device test iC-Haus device test iC-Haus device test iC-Haus device test iC-Haus device test TMA Code 0x00 0x01 Notes Adr 0x06, Bit 0 Pin A A COS+ Pin B B COSPin SDA SDA SIN+ Pin SCL SCL SIN-
To permit the verification of GAIN and OFFSET settings, the input amplifier outputs are available at the pins. To operate the converter a signal of 4 Vpp is the ideal here and should not be exceeded. Pin loads above 1 M are adviceable for accurate measurements.
Table 30: Analog Test Mode
Table 29: Test Mode Parameter GAIN ideally adjusts the signal levels to ca. 4 Vpp and should not be touched afterwards.
5V A: COS+ SDA: Sin+
Both scope display modes are feasible for OFFS (positive values) or RATIO adjustments; regarding the adjustment of PHASE the X/Y mode may be preferred. For OFFS adjustment towards negative values the test signals COS- (pin B) and SIN- (pin SCL) are relevant.
0V
Y/T 1 V/Div vert.
X/Y 1 V/Div vert. 1 V/Div hor.
Figure 17: Calibrated signals with TMA mode.
IC-NQ
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev D1, Page 19/25 BiSS INTERFACE Serial BiSS communication differentiates between the fast cyclic transmission of sensor data for the output of angle position and period counter data and the transmission of register data which can include bidirectional read and write access. The required mode of communication is initiated by the interface master; as a slave IC-NQ determines up to which maximum clock interval the selected mode is retained. Sensor mode timeout ttos and register mode timeout ttor thus give the master a minimum clock frequency of fclk(MA)min.
CFGTOS Code 0x00 0x01 0x02 0x03 CFGTOR Code 0x00 0x01 0x02 0x03 Notes Adr 0x06, Bit 5:4 Timeout ttos Sensor mode typ. 128 s typ. 16 s typ. 4 s typ. 1 s Adr 0x06, Bit 7:6 Timeout ttor Regist. mode typ. 1 ms typ. 256 s typ. 32 s not permitted Ref. clock counts 2049-2060 513-514 67-68 -
32 fosc
Protocol and Data Format
Ref. clock counts 256-259 32-35 8-11 2-5
fclk(MA) min*
Figure 18: BiSS B Protocol
11 kHz 88 kHz 352 kHz 1.41 MHz fclk(MA) min* 1.4 kHz 5.5 kHz 42 kHz - Single-Cycle Data Channel: SCD Type Label Bits 0, 8 0,8, 12, 24* 3...13 1 1 5 6* DATA ERROR ERROR CRC CRC DATA Period Counter P(7:0) Period Counter P(23:0)* (multiturn position) Angle Data S(12:0): 3 to 13 bits (singleturn position) Error bit E1 (amplitude error) Error bit E0 (frequency error) Polynomial 0x25 x5 + x2 + x0 (inverted bit output) Polynomial 0x43* x6 + x1 + x0 (inverted bit output) Label
A ref. clock count is equal to (see El. Char. A01 ). The permissible max. clock frequency is specified by item E06 .
Table 31: Interface Timeouts
M2S Code 0x00 0x01 0x00 0x01 0x02 0x03 Notes Adr 0x00, Bit 6:5 SCD* SCD CRC Poly. MCD not in use
Multicycle Data Channel: MCD - not in use Bits 1 Bits 3 7 1 4 Type zero bit Type ID ADR WNR CRC Adr 8 0x10.. 1F 0x20.. 77 0x78.. 7F 4 CRC Label Slave ID Register Address Write-Not-Read Command Polynomial 0x13 x4 + x1 + x0 (inverted bit output) Content Device Configuration Data OEM Daten BiSS Identifier Polynomial 0x13 x4 + x1 + x0 (inverted bit Output)
Register Data Channel: CD
Chip releases IC-NQ X2, IC-NQ X3: 0x25 1 zero bit P(7:0) 0x25 1 zero bit 1 zero bit 1 zero bit 1 zero bit n/a Chip release IC-NQ V2: 0x25 P(7:0) P(11:0) P(23:0) 0x25 0x43 0x43
*) Period counter output via SCD
Table 32: Period Counter Output
BiSSMOD Code 0x00 0x01 Adr 0x00, Bit 7 Version B C Description BiSS B without multicycle data Transparency for BiSS C
Table 34: BiSS Data Channels *) For chip release IC-NQ V2
Table 33: Protocol Version
IC-NQ
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev D1, Page 20/25 Sensor Data Communication
The sensor data produced by IC-NQ contains 3 to 13 bits of angle value (S), the period counter (P) with up to 24 bits (optional), 2 bits of error messages (E1, E0), and 5 CRC bits (C). Here, M2S sets the output enable for the position counter; the counter bits, with the MSB leading, are transmitted in front of the angle value. The 5 bit CRC output is based on the polynomial 0x25 (100101b), the 6 bit CRC output on the polynomial 0x43 (1000011b) and comes active with longer SCD data. Generally, CRC bits are output inverted. As soon as the storage of sensor data is initiated Latch conversion is paused for one MA clock cycle. This time must be taken into consideration when calculating the maximum input frequency. The synchronization output at Z (CFGZ = 0x02) is stored until the start bit of the previous slave arrives.
SCD: Angle data Bits 13 2 5 1 Config. Type DATA ERROR CRC Zero bit SELRES = 0x03, M2S = 0x00 Label Angle Data S(12:0) Error bits E1, E0 Polynomial 0x25
Figure 19: BiSS B protocol
Figure 20: BiSS C protocol transparency, no interpretation of CDM Register Data Communication
For as long as the configuration error is active the longest timeout is used for the register mode independent of CFGTOR. Thus when configuring via BiSS CFGTOR and RPL should be written before address 0. A write access at Address 0 triggers an internal reset. This allows the period counter to be set to zero and configuration errors to be reset; the EEPROM is not read out a second time. Register access via BiSS can be limited using the programming bits RPL according to the following table.
RPL RPL Adr 0x03, Bit 3:2 Configuration Address 0-31 Read / Write Read User Address 32-119 Read / Write Read / Write Read / Write Read BiSS Identifier Address 120-127 Read / Write Read Read Read
Table 35: Format example 1
SCD: Angle data with 8-bit period counter Bits 8 13 2 5 1 Config. Typ DATA DATA ERROR CRC Zero bit SELRES = 0x03, M2S = 0x01 Label Period Counter S(7:0) Angle Data S(12:0) Error Bits E1, E0 Polynomial 0x25
0x00 0x01 0x02 0x03
Table 36: Format example 2
Table 37: Register Access Safety Level
IC-NQ
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev D1, Page 21/25 Sensor Data Output in SSI Format With SELSSI = 1 the communication timing is switched to SSI compatibility. Data output is in binary format starting with the MSB. It can be configured if the error bits are to be send afterwards.
CFGSSI Code 0x00 0x01 0x02 0x03 Adr 0x03, Bit 7:6 Additional bits E1, E0, zero bit none E1, E0, zero bit none Ring register operation no no yes yes
Table 38: SSI Output Examples of SSI formats
SSI Output Formats 13-bit SSI Res Mode Error CRC X Example 13 bit SSI
*1
T1 S9
T2 S8
T3 S7
T4... T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 S6 ... S0 E1 S2 E0 S1 0 0 S0
Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop
10 bit SSI
0
0
0
0
0
0
0
0
0
0
0
0
Example
S12 S11 S10 S9 ... S3
Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop
0 S12 S11 S10 S9 ... S3 S2 S1 S0
0
0
0
0
0 S8
0 S7
0 S6
0 S5
0 S4
0 S3
0 S2
SSI-R *2
Example
Stop S12 S11 S10 S9
0 S12 S11 S10 S9 ... S3 P7 P6 P5 S2 S1 S0 S8 E1 S7 E0 S6 0 0 P4 ... P0, S10 S9 S12, S11 S5
Stop Stop Stop Stop Stop Stop Stop Stop Stop
25-bit SSI 13 bit SSI 8 + 13 SSI bit*3 X X Example Example Configuration Input SLI = 0, SELSSI = 1 CFGMCD = 0x00, CFGSSI = 0x00, unless otherwise noted. *1 CFGSSI = 0x01; *2 CFGSSI = 0x03; *3 CFGMCD = 0x01 Caption SSI protocol SSI ring operation 0 S4 0 S3 0 S2 0 S1 0 S0 0 E1 0 E0 0 0 0 0
Stop
0
Table 39: SSI Output Formats
EEPROM INTERFACE Serial EEPROM components permitting operation from 3.3 V to 5 V can be connected (such as 24C02, for example). When the device is switched on the memory area of bytes 0 to 15 is mapped onto IC-NQ's registers. The higher memory areas, bytes 16-111, are readily available to the system via BiSS. The EEPROM addresses 0-111 are mapped onto the BiSS addresses 16-127. If no EEPROM is connected the device must be configured via BiSS and address 0 written last. In this case IC-NQ does not respond to addresses 16119; reading addresses 120-127 sends the device ID plus the contents of register 0 to address 124.
IC-NQ
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev D1, Page 22/25 APPLICATION HINTS Principle Input Circuits
PSIN + 11 App + RS1 25kS 1Vss to 120S S PSIN VREF RS 120S NSIN NSIN + INPUT SIN VREF NSIN RS2 25kS NSIN + INPUT SIN PSIN
PSIN
SENSOR
case
IC-NQ
SENSOR
case
IC-NQ
Figure 22: Input circuit for current signals of 11 A.
Figure 21: Input circuit for voltage signals of 1 Vpp with no ground reference. When grounds are not separated the connection NSIN to VREF must be omitted.
R3 1kS R1 1kS R2 1kS + R4 1kS PSIN +
+5V R001 1kS R002 1kS -
PSIN +
V-GEN 1Vpp
NSIN + INPUT SIN VREF
V-GEN 2Vpp NSIN
-
+ INPUT SIN VREF
IC-NQ
Figure 23: Input circuit for single-side voltage or current source signals with ground reference (adaptation via resistors R3, R4).
R1 10kS
IC-NQ
Figure 24: Simplified input wiring for single-side voltage signals with ground reference.
+TTL -TTL or open 5kS RS3 1kS PSIN +
-
5kS
PSIN +
+SIN
+ R2 10kS
120S -SIN
RS1 5kS RS2 5kS
CS1 220pF RS4 1kS NSIN +
GAIN= 10
Ip 10 App
In 10 App NSIN
-
INPUT SIN
+ INPUT SIN VREF
ENCODER
VREF case CS2 47nF
IC-NQ
IC-NQ
Figure 25: Input circuit for differential current sink sensor outputs, eg. using Opto Encoder iC-WG.
Figure 26: Combined input circuit for 11 A, 1 Vpp (with 120 termination) or TTL encoder signals. RS3/4 and CS1 serve as protection against ESD and transients.
IC-NQ
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev D1, Page 23/25 Basic circuit
Figure 27: Basic circuit for evaluation of magneto-resistor bridge sensors.
EVALUATION BOARD The IC-NQ device is equipped with an evaluation board for test purposes; descriptions are available separately.
IC-NQ
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev D1, Page 24/25 DESIGN REVIEW: Notes On Chip Functions
IC-NQ X2 IC-NQ X3 No. 1 Function, Parameter/Code SELRES Illegal setting: 0x0E for resolution 4 Description and Application Hints A minimal resolution of 8 is required for the frequency monitoring function and period counting as well. Thus, a binary resolution of 4 is not permitted when using the period counter and the serial interface for data output with the BiSS or SSI protocol. A resolution of 4 may be used for solely incremental applications with A/B/Z output, what then requires the deactivation of the frequency monitoring function (by FERR set to 0x00). 2 ZPOS Illegal settings: 0x01...0x07, 0x09...0x0F, 0x11...0x17, 0x19...0x1F Illegal settings of ZPOS delay accurate converter operation following power on. Depending on the sin/cos input signals (phase angle) the A/B outputs can provide pulses causing an external counter to alternately count up and down. This may disturb the startup of a drive if the motion controller tolerates only single A/B edges during standstill checking. The converter operation is again accurate when the sin/cos input signals have changed, by a maximum of 45 angular degrees. 3 M2S Illegal settings: 0x02, 0x03 Illegal settings, enabling a period counter output of 12 or 24 bits, may cause position data jumping with fast changes in the direction of count (e.g. applications with length gauges). It is thus advisable to use 8-bit period counting (M2S 0x01) and to capture the overflow in the external microcontroller.
Table 40: Notes on chip functions regarding IC-NQ chip releases X2, X3
IC-NQ V2 No. 1 2 Function, Parameter/Code SELRES Description and Application Hints See description given for IC-NQ X2, X3 No further exclusions known at time of printing.
Table 41: Notes on chip functions regarding IC-NQ chip release V2
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IC-NQ
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev D1, Page 25/25 ORDERING INFORMATION
Type IC-NQ
Package TSSOP20 4.4 mm
Order Designation IC-NQ TSSOP20 IC-NQ TSSOP20 ET -40/125 IC-NQ EVAL NQ1D
Evalutaion Board
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